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REPUBLIC OF SERBIA MINISTRY OF DEFENCE
MINISTRY OF DEFENCE Material Resources Sector Defensive Technologies Department
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An Implementation of SDH Framer/Deframer on FPGA
Vladimir MarinkoviĆ Faculty of Technical Sciences at University of Novi Sad, Novi Sad, Vladimir.Marinkovic@rt-rk.com NIKOLA VRANIĆ RT-RK Computer Based Systems LLC, Novi Sad, Nikola.Vranic@rt-rk.com Miroslav DimitraskoviĆ RT-RK Computer Based Systems LLC, Novi Sad, Miroslav.Dimitraskovic@rt-rk.com NIKOLA TESLIĆ Faculty of Technical Sciences at University of Novi Sad, Novi Sad, Nikola.Teslic@rt-rk.com
Abstract: Increasing number of devices involved in communications and their need to stay connected accompanied by even greater need to exchange huge amounts of data require new media for data transfer with much higher throughputs. Nowadays, the fastest medium for transferring data is a single fiber optic cable. This medium introduces different multiplexing protocols for transferring multiple digital bit streams such as Plesiochronous Digital Hierarchy (PDH) and its successor Synchronous Digital Hierarchy (SDH). In addition, there is a need for intercepting and demultiplexing frames of these protocols with the goal of data processing or transferring to other levels of the multiplex. This paper presents a solution for framing/deframing of SDH at different speeds with a simple interface for further processing of payloads or headers. A pipelined processing flow is proposed for extracting frames or virtual containers of different levels, including different operations like SDH pointer processing, demultiplexing, dealigning, calculation of Bit Interleaved Parity code of N bits (BIP-N), etc. After being processed, frames or containers are packed by inverse operations, or they may be used at later stage for transitions to other multiplex levels. Key words: Synchronous Digital Hierarchy (SDH), FPGA, framing, deframing.
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